SH7713 datasheet(273/904 Pages) RENESAS

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Section 7 X/Y Memory

Rev.1.50 Aug. 30, 2006 Page 233 of 860

REJ09B0288-0150

Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The X/Y memory can be accessed by the

DSP directly from space P2. The MMU can be used to map the logical addresses in spaces P0 and

P3 to this memory.

User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the DSP

directly from space Uxy. The MMU can be used to map the logical addresses in space U0 to this

memory.

7.2.3

Access from DMAC and E-DMAC

The X/Y memory is always accessed by the DMAC and E-DMAC via the I bus, which is a

physical address bus. Addresses in which the upper three bits are 0 in addresses shown in table 7.1

must be used.

7.3

Usage Notes

7.3.1

Page Conflict

In the event of simultaneous accesses to the same page from different buses, the conflict on the

pages occurs. Although each access is completed correctly, this kind of conflict tends to lower

X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such

conflict as far as possible. For example, conflict will not arise if different memory or different

pages are accessed by each bus.

7.3.2

Bus Conflict

The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I

bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of

conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software

measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory

by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be

prevented.

7.3.3

MMU and Cache Settings

When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct

operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled

(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If

the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory

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