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SH7713 Datasheet(PDF) 276 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 276 Page - Renesas Technology Corp |
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276 / 904 page ![]() Section 8 Interrupt Controller (INTC) Rev.1.50 Aug. 30, 2006 Page 236 of 860 REJ09B0288-0150 DMAC SCIF0/1 E-DMAC SIOF0/1 TMU RTC WDT REF H-UDI 8 Input/output control Priority identifier Com- parator Interrupt request SR CPU Bus interface Interrupt controller I3 I2 I1 I0 (Interrupt request) ICRn IRRn IRQ5 to IRQ0 NMI IRQOUT IPRn [Legend] DMAC: SCIF0/1: E-DMAC: SIOF0/1: TMU: RTC: WDT: REF: H-UDI: ICRn: IPRn: IRRn: SR: Direct memory access controller Serial communication interface with FIFO Direct memory access controller for ethernet controller Serial I/O with FIFO Timer unit Realtime clock unit Watchdog timer Refresh request in bus state controller User-debugging interface Interrupt control registers 0, 1 Interrupt priority registers A to I Interrupt request registers 0 to 5, 7 and 8 Status register IRL3 to IRL0 4 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Figure 8.1 Block Diagram of INTC |
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