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SH7713 Datasheet(PDF) 274 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 274 Page - Renesas Technology Corp |
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274 / 904 page  Section 7 X/Y Memory Rev.1.50 Aug. 30, 2006 Page 234 of 860 REJ09B0288-0150 via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus, several cycles are necessary (the number of necessary cycles varies according to the ratio between the internal clock (I φ) and bus clock (Bφ) or the operation state of the DMAC and E-DMAC). In a program that requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The relationship described above is summarized in table 7.2. Table 7.2 MMU and Cache Settings Setting Logical Address Space and Access Enabled or Disabled CCR1.CE MMUCR.AT P0, U0 P1 P2, Uxy P3 0 0 B B A B 0 1 B B A B 1 0 X X A X 1 1 C X A C [Legend] A: Accessible (recommended) B: Accessible C: Accessible (Note that MMU page attribute must be specified as cache disabled by clearing the C bit to 0.) X: Not Accessible 7.3.4 Sleep Mode In sleep mode, I bus master modules such as the DMAC and E-DMAC cannot access the X/Y memory. 7.3.5 Address Error If writing that may causes an address error is performed on the X/Y memory, the contents of the X/Y memory are not guaranteed. |
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