SH7721 datasheet(430/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 368 of 1458

REJ09B0033-0300

When bank active mode is set, if only accesses to the respective banks in the area 3 space are

considered, as long as accesses to the same row address continue, the operation starts with the

cycle in figure 9.19 or 9.22, followed by repetition of the cycle in figure 9.20 or 9.23. An access to

a different area during this time has no effect. If there is an access to a different row address in the

bank active state, after this is detected the bus cycle in figure 9.21 or 9.24 is executed instead of

that in figure 9.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh

cycle or after the bus is released as the result of bus arbitration.

Tc4

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

DACKn*2

Tc2

Tc3

Tc1

Td4

Td2

Td3

Td1

Tde

A12/A11*1

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Notes:

Figure 9.19

Burst Read Timing (No Auto-Precharge)

SH7721 Datasheet(PDF) 430 Page - Renesas Technology Corp