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SH7721 Datasheet(PDF) 428 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 428 Page - Renesas Technology Corp

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Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 366 of 1458
REJ09B0033-0300
(6)
Single Write
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
Figure 9.18 shows the single write basic timing.
CKIO
A25 to A0
CSn
RD/
WR
RAS
DQMxx
D31 to D0
BS
Tap
DACKn*2
Tr
Tc1
Trwl
A12/A11*1
CAS
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Notes:
Figure 9.18
Basic Timing for Single Write (Auto-Precharge)



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