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SH7721 Datasheet(PDF) 425 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 425 Page - Renesas Technology Corp |
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425 / 1524 page  Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 363 of 1458 REJ09B0033-0300 (4) Single Read A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in SDRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Figure 9.16 shows the single read basic timing. CKIO A25 to A0 CSn RD/ WR RAS DQMxx D31 to D0 BS Tap DACKn*2 Tr Tc1 Tde Td1 A12/A11*1 CAS 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Notes: Figure 9.16 Basic Timing for Single Read (Auto-Precharge) |
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