SH7721 datasheet(423/1524 Pages) RENESAS

423 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 361 of 1458

REJ09B0033-0300

In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM

in variable frequencies. Figure 9.15 shows an example in which wait cycles are inserted. The

number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where

the READA command is output can be specified using the TRCD1 and TRCD0 bits in CS3WCR.

If the TRCD1 and TRCD0 bits specify two cycles or more, a Trw cycle where the NOT command

is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle

where the READA command is output to the Td1 cycle where the read data is latched can be

specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in

CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number

of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency

for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency

in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a

latch circuit between this LSI and the synchronous DRAM.

Tc4

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tap

DACKn*2

Tc2

Tc3

Tc1

Td4

Tde

Td2

Td3

Td1

A12/A11*1

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Notes:

Figure 9.14

Burst Read Basic Timing (Auto-Precharge)

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