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SH7721 Datasheet(PDF) 457 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 457 Page - Renesas Technology Corp |
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457 / 1524 page  Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 395 of 1458 REJ09B0033-0300 Tpcm1w CKIO A25 to A0 CExx RD/ WR RD D15 to D0 WE D15 to D0 BS Read Write Tpcm2 Tpcm0 Tpcm1 Tpcm1w Tpcm0w Tpcm2w Tpcm1w Tpcm1w WAIT Figure 9.39 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) If all 32 Mbytes of the memory space are used as an IC memory card interface, the REG signal that switches between the common memory and attribute memory can be generated by an I/O port. If the memory space used for the IC memory card interface is 16 Mbytes or less, the A24 pin can be used as the REG signal by using the memory space as a 16-Mbyte common memory space and a 16-Mbyte attribute memory space. |
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