SH7721 datasheet(515/1524 Pages) RENESAS

515 / 1524 page

Section 11

Clock Pulse Generator (CPG)

Rev. 3.00 Jan. 18, 2008 Page 453 of 1458

REJ09B0033-0300

Section 11

Clock Pulse Generator (CPG)

This LSI has a clock pulse generator which generates an internal clock (I

φ), a peripheral clock

φ), and a bus clock (Bφ). The clock pulse generator consists of oscillators, PLL circuits, and a

divider.

11.1

Features

The CPG has the following features:

• Four clock modes: Selection of four clock modes according to the frequency range to be used

and direct connection of crystal resonator or external clock input.

• Three clocks generated independently: An internal clock for the CPU and cache (Iφ); a

peripheral clock (P

φ) for the on-chip supporting modules; and a bus clock (Bφ=CKIO) for the

external bus interface.

• Frequency change function: Internal and peripheral clock frequencies can be changed

independently using the PLL circuit and divider circuit within the CPG. Frequencies are

changed by software using frequency control register (FRQCR) settings.

• Power-down mode control: The clock can be stopped for sleep mode and standby mode and

specific modules can be stopped using the module standby function.

SH7721 Datasheet(PDF) 515 Page - Renesas Technology Corp