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SH7721 Datasheet(PDF) 908 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 908 Page - Renesas Technology Corp

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Section 25
USB Function Controller (USBF)
Rev. 3.00 Jan. 18, 2008 Page 846 of 1458
REJ09B0033-0300
25.4.5
EP2 Bulk-In Transfer (Dual FIFOs)
USB function
Application
IN token reception
Data transmission to host
Clear EP2 transfer
request flag
(IFR0/EP2 TR = 0)
Enable EP2 FIFO
empty interrupt
(IER0/EP2 EMPTY = 1)
IFR0/EP2 EMPTY
interrupt
Write one packet of data
to EP2 data register
(EPDR2)
Write 1 to EP2 packet
enable bit
(TRG/EP2 PKTE = 1)
Set EP2
empty status
(IFR0/EP2
EMPTY = 1)
Valid data
in EP2 FIFO?
NAK
ACK
Interrupt request
Yes
No
Clear EP2 empty status
(IFR0/EP2 EMPTY = 0)
Space
in EP2 FIFO?
No
Yes
Interrupt
request
Figure 25.12
EP2 Bulk-In Transfer Operation
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes
without being aware of this dual-FIFO configuration. However, one data write is performed for
one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at
one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64-
byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an IFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the IER0/EP2
EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty,
and so an EP2 FIFO empty interrupt is generated immediately.



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