SH7721 datasheet(967/1524 Pages) RENESAS

967 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 905 of 1458

REJ09B0033-0300

26.4.3

Color Palette Specification

(1)

Color Palette Register

This LCDC has a color palette which outputs 24 bits of data per entry and is able to

simultaneously hold 256 entries. The color palette thus allows the simultaneous display of 256

colors chosen from among 16-M colors.

The procedure below may be used to set up color palettes at any time.

1. The PALEN bit in the LDPALCR is 0 (initial value); normal display operation

2. Access LDPALCR and set the PALEN bit to 1; enter color-palette setting mode after three

cycles of peripheral clock.

3. Access LDPALCR and confirm that the PALS bit is 1.

4. Access LDPR00 to LDPRFF and write the required values to the PALD00 to PALDFF bits.

5. Access LDPALCR and clear the PALEN bit to 0; return to normal display mode after a cycle

of peripheral clock.

A 0 is output on the LCDC display data output (LCD_DATA) while the PALS bit in LDPALCR is

set to 1.

Color

Monochrome

Figure 26.3

Color-Palette Data Format

PALDnn color and gradation data should be set as above.

For a color display, PALDnn[23:16], PALDnn[15:8], and PALDnn[7:0] respectively hold the R,

G, and B data. Although the bits PALDnn[18:16], PALDnn[9:8], and PALDnn[2:0] exist, no

memory is associated with these bits. PALDnn[18:16], PALDnn[9:8], and PALDnn[2:0] are thus

not available for storing palette data. The numbers of valid bits are thus R: 5, G: 6, and B: 5. A 24-

bit (R: 8 bits, G: 8 bits, and B: 8 bits) data should, however, be written to the palette-data registers.

When the values for PALDnn[23:19], PALDnn[15:10], or PALDnn[7:3] are not 0, 1 or 0 should

be written to PALDnn[18:16], PALDnn[9:8], or PALDnn[2:0], respectively. When the values of

PALDnn[23:19], PALDnn[15:10], or PALDnn[7:3] are 0, 0s should be written to

PALDnn[18:16], PALDnn[9:8], or PALDnn[2:0], respectively. Then 24 bits are extended.

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