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SH7721 Datasheet(PDF) 990 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 990 Page - Renesas Technology Corp |
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990 / 1524 page  Section 26 LCD Controller (LCDC) Rev. 3.00 Jan. 18, 2008 Page 928 of 1458 REJ09B0033-0300 26.6 Usage Notes 26.6.1 Procedure for Halting Access to Display Data Storage VRAM (Synchronous DRAM in Area 3) Follow the procedure below to halt access to VRAM for storing display data (synchronous DRAM in area 3). • Procedure for Halting Access to Display Data Storage VRAM A. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1. B. Clear the DON bit in LDCNTR to 0 (display-off mode). C. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0. D. Wait for the display time for a single frame to elapse. This halting procedure is required before selecting self-refreshing for the display data storage VRAM (synchronous DRAM in area 3) or making a transition to standby mode or module standby mode. |
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