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SH7721 Datasheet(PDF) 1005 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 1005 Page - Renesas Technology Corp |
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1005 / 1524 page ![]() Section 27 A/D Converter Rev. 3.00 Jan. 18, 2008 Page 943 of 1458 REJ09B0033-0300 Table 27.3 A/D Conversion Time (Single Mode) CKS1 = 1, CKS0 = 0 CKS1 = 0, CKS0 = 1 CKS1 = 0, CKS0 = 0 Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start delay t D 18 21 10 13 6 9 Input sampling time t SPL 129 65 33 A/D conversion time t CONV 535 545 275 285 141 151 Note: Values in the table are numbers of states (t cyc) for Pφ. 27.4.5 External Trigger Input Timing The A/D conversion can also be started by the external trigger input. The external trigger input is enabled at the ADTRG pin when bits TRGE1 and TRGE0 in A/D control register (ADCR) are set to 1. The falling edge of ADTRG input pin sets the ADST bit in the A/D control/status register (ADCSR) to 1, and then A/D conversion is started. Other operations are the same as when the ADST bit is set to 1 by software, regardless of the conversion mode. Figure 27.6 shows the timing. P φ ADTRG External trigger signal ADST A/D converter Figure 27.6 External Trigger Input Timing |
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