SH7721 datasheet(1047/1524 Pages) RENESAS

1047 / 1524 page

Section 29

PC Card Controller (PCC)

Rev. 3.00 Jan. 18, 2008 Page 985 of 1458

REJ09B0033-0300

29.5

Usage Notes

(1)

External Bus Frequency Limit when Using PC Card

According to the PC card standard, the attribute memory access time is specified as 600 ns (3.3

V)/300 ns (5 V). Therefore, when this LSI accesses attribute memory, the bus cycle must be

coordinated with the PC card interface timing. In this LSI, the timing can be adjusted by setting

the TED, TEH, and PCW values in the CS6BWCR register, allowing a PC card to be used within

the above frequency ranges.

The common memory access time and I/O access time (based on the

(IORD) and (IOWR) signals)

are also similarly specified (see table below), and a PC card must be used within the above ranges

in order to satisfy all these specifications.

PC Card Space

Access Time (5 V Operation)

Access Time (3.3 V Operation)

Attribute memory

300 ns

600 ns

Common memory

250 ns

600 ns

I/O space (pulse width of

IORD and IOWR)

165 ns

(2)

Pin Function Control and Card Type Switching

When setting pin function controller pin functions to dedicated PC card use ("other function"), the

disabled state should first be set in the card status change interrupt enable register

(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the

setting has been made. However, this restriction does not apply to the card detection pins (

CD1

and

CD2).

When changing the card type bit (P0PCCT) in the area 6 general control register (PCC0GCR), the

disabled state should first be set in the card status change interrupt enable register

(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the

setting has been made.

Reason: When PC card controller settings are modified, the functions of PC card pins that

generate various interrupts change, with the result that unnecessary interrupts may be

generated.

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