SH7721 datasheet(147/1524 Pages) RENESAS

147 / 1524 page

Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 85 of 1458

REJ09B0033-0300

(1)

Extension of Status Register (SR)

In DSP mode, the following control bits are added to the status register (SR). These added bits are

called DSP extension bits. These DSP extension bits are valid only in DSP mode.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 28



For details, refer to section 2, CPU.

27 to 16

RC11 to

RC0

All 0

R/W

Repeat Counter

Holds the number of repeat times in order to perform

loop control, and can be modified in privileged mode,

privileged DSP mode, or user DSP mode. At reset, this

bit is initialized to 0. This bit is not affected in the

exception handling state.

15 to 13



For details, refer to section 2, CPU.

DSP

R/W

DSP Bit

Enables or disables the DSP extended functions. If

this bit is set to 1, the DSP extended functions are

enabled. This bit can be modified in privileged mode,

privileged DSP mode, or user DSP mode. At reset, this

bit is initialized to 0. This bit is not affected in the

exception handling state.

MDY

MDX

R/W

Modulo Control Bits

Enable or disable modulo addressing for X/Y memory

access. These bits can be modified in privileged mode,

privileged DSP mode, or user DSP mode. At reset,

these bits are initialized to 0. These bits are affected in

the exception handling state.

9 to 4



For details, refer to section 2, CPU.

FR1

FR0

R/W

Repeat Flag Bits

Used by repeat control instructions. These bits can be

modified in privileged mode, privileged DSP mode, or

user DSP mode. At reset, these bits are initialized to 0.

These bits are affected in the exception handling state.

1, 0



For details, refer to section 2, CPU.

Note:

When data is written to the SR register, 0 should be written to bits that are specified as 0.

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