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SH7721 Datasheet(PDF) 149 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 149 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 87 of 1458
REJ09B0033-0300
Table 3.3
Operation of SR Bits in Each Processing Mode
Privileged
Mode
User Mode
Privileged
DSP Mode
User DSP
Mode
Field
MD = 1 &
DSP = 0
MD = 0 &
DSP = 0
MD = 1 &
DSP = 1
MD = 0 &
DSP = 1
Access to
DSP-Related
Bit with
Dedicated
Instruction
Initial Value
after Reset
MD
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RB
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
BL
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RC [11:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
SETRC
instruction
000000000000
DSP
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
0
DMY
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
0
DMX
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
0
Q
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
M
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
I[3:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1111
RF[1:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
SETRC
instruction
x
S
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
T
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
[Legend]
S:
STC instruction
L:
LDC instruction
OK:
STC/LDC operation is enabled.
Invalid instruction:
Exception occurs when an invalid instruction is executed.
NG:
Previous value is retained. No change.
x:
Undefined



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