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SH7721 Datasheet(PDF) 153 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 153 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 91 of 1458
REJ09B0033-0300
• Example 2: Repeat loop consisting of three instructions
LDRS RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RS register
LDRE RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==0 during SETRC instruction
execution, the repeat loop is regarded
as three-instruction repeat.
RptDtct:
instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
; [Repeat start instruction]
Instr2
;
RptEnd:
instr3
; [Repeat end instruction]
• Example 3: Repeat loop consisting of two instructions
LDRS RptDtct +6; Sets (repeat detection instruction
address + 6) to the RS register
LDRE RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==-2 during SETRC instruction
execution, the repeat loop is regarded
as two-instruction repeat.
RptDtct:
instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
; [Repeat start instruction]
RptEnd:
instr2
; [Repeat end instruction]



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