SH7721 datasheet(157/1524 Pages) RENESAS

157 / 1524 page

Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 95 of 1458

REJ09B0033-0300

• Example 6: Repeat loop consisting of three instructions (extended to the instruction stream

shown in example 2, above)

REPEAT RptStart, RptEnd, #4

instr0

;

RptStart: instr1

; [Repeat start instruction]

instr2

;

RptEnd:

instr3

; [Repeat end instruction]

• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream

shown in example 3, above)

REPEAT RptStart, RptEnd, #4

instr0

;

RptStart: instr1

; [Repeat start instruction]

RptEnd:

instr2

; [Repeat end instruction]

• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction

stream shown in example 4, above)

REPEAT RptStart, RptEnd, #4

instr0

;

RptStart:

RptEnd:

instr1

; [Repeat start instruction]==[Repeat end

instruction]

In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE

registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC

and STC instructions for the SR register. These instructions should be used if an exception is

enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS

and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception

handling and by restoring the stored values after exception handling. However, note that there are

some restrictions on exception acceptance during repeat loop execution. For details refer to

Restrictions on Repeat Loop Control in section 3.3.1, DSP Repeat Control and section 7,

Exception Handling.

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