SH7721 datasheet(159/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 97 of 1458

REJ09B0033-0300

(c)

Instructions prohibited during repeat loop (In a repeat loop consisting of four or more

instructions)

The following instructions must not be placed between the repeat start instruction and repeat

detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the

correct operation cannot be guaranteed.

• Repeat control instructions

SETRC, LDRS, LDRE

• Load instructions for SR, RS, and RE registers

LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS

Note:

Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control

instructions, and the external loop by other instructions such as DT or BF/S.

(d)

Branching to an instruction following the repeat detection instruction and restriction

on an exception acceptance

Execution of a repeat detection instruction must be completed without any branch so that the CPU

can recognize the repeat loop. Therefore, when the execution branches to an instruction following

the repeat detection instruction, the control will not be passed to a repeat start instruction after

executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this

case, the RC[11:0] bits of the SR register will not be changed.

• If a conditional branch instruction is used in the repeat loop, an instruction before a repeat

detection instruction must be specified as a branch destination.

• If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call

instruction must be placed before a repeat detection instruction.

Here, a branch includes a return from an exception processing routine. If an exception whose

return address is placed in an instruction following the repeat detection instruction occurs, the

repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted

from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts

that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a

transition to an exception occurs but a program cannot be returned to the previous execution state

correctly. For details, refer to section 7, Exception Handling.

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