SH7721 datasheet(163/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 101 of 1458

REJ09B0033-0300

X memory

DSP unit

XDB

[15:0]

XAB

[15:0]

CPU

YAB

[15:0]

CDB

[31:0]

DSR

A0G

A1G

LAB

[31:0]

LDB

[31:0]

YDB

[15:0]

Y memory

Legend

XAB

XDB

YAB

YDB

LAB

LDB

CDB

: X bus (address)

: X bus (data)

: Y bus (address)

: Y bus (data)

: L bus (address)

: L bus (data)

: C bus (data)

Figure 3.4 DSP Registers and Bus Connections

(1) Double data transfer instructions (MOVX.W, MOVY.W)

With double data transfer instructions, X memory and Y memory can be accessed in parallel.

In this case, the specific buses called X bus and Y bus are used to access X memory and Y

memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict

occurs among X, Y, and L buses.

Load instructions for X memory specify the X0 or X1 register as the destination operand. Load

instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers

for X or Y memory specify the A0 or A1 register as the source operand. These instructions use

only word data (16 bits). When a word data transfer instruction is executed, the upper word of

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