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SH7721 Datasheet(PDF) 165 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 165 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 103 of 1458
REJ09B0033-0300
(3) System control instructions
The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system
registers. Accordingly, data transfer operations between these DSP system registers and general
registers or memory can be executed by the STS and LDS instructions. These DSP system
registers can be treated as the CPU system register such as PR, MACH and MACL and can use the
same addressing modes.
Table 3.9
Extended System Control Instructions in DSP Mode
Instruction
Operation
Execution States
STS
DSR,Rn
DSR
→ Rn
1
STS
A0,Rn
A0
→ Rn
1
STS
X0,Rn
X0
→ Rn
1
STS
X1,Rn
X1
→ Rn
1
STS
Y0,Rn
Y0
→ Rn
1
STS
Y1,Rn
Y1
→ Rn
1
STS.L
DSR,@-Rn
Rn – 4
→ Rn, DSR → (Rn)
1
STS.L
A0,@-Rn
Rn – 4
→ Rn, A0 → (Rn)
1
STS.L
X0,@-Rn
Rn – 4
→ Rn, X0 → (Rn)
1
STS.L
X1,@-Rn
Rn – 4
→ Rn, X1 → (Rn)
1
STS.L
Y0,@-Rn
Rn – 4
→ Rn, Y0 → (Rn)
1
STS.L
Y1,@-Rn
Rn – 4
→ Rn, Y1 → (Rn)
1
LDS.L
@Rn+,DSR
(Rn)
→ DSR, Rn + 4 → Rn
1
LDS.L
@Rn+,A0
(Rn)
→ A0, Rn + 4 → Rn
1
LDS.L
@Rn+,X0
(Rn)
→ X0, Rn + 4 → Rn
1
LDS.L
@Rn+,X1
(Rn)
→ X1, Rn + 4 → Rn
1
LDS.L
@Rn+,Y0
(Rn)
→ Y0, Rn + 4 → Rn
1
LDS.L
@Rn+,Y1
(Rn)
→ Y1, Rn + 4 → Rn
1
LDS
Rn,DSR
Rn
→ DSR
1
LDS
Rn,A0
Rn
→ A0
1
LDS
Rn,X0
Rn
→ X0
1
LDS
Rn,X1
Rn
→ X1
1
LDS
Rn,Y0
Rn
→ Y0
1
LDS
Rn,Y1
Rn
→ Y1
1



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