SH7721 datasheet(164/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 102 of 1458

REJ09B0033-0300

Double data transfer instructions can be described in parallel to the DSP operation instructions.

Even if a conditional operation instruction is specified in parallel to a double data transfer

instruction, the specified condition does not affect the data transfer operations. For details, refer to

section 3.5, DSP Data Operation Instructions.

Double data transfer instructions can access only the X memory or Y memory and cannot access

other memory space. The X bus and Y bus are 16 bits and support 64-byte address spaces

corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF,

respectively. Because these areas are included in the P2/Uxy area, they are not affected by the

cache and address translation unit.

(2) Single data transfer instructions

The single data transfer instructions access any memory location. All DSP registers other than the

DSR can be specified as source and destination operands.* Guard bit registers A0G and A1G can

also be specified as two independent registers. Because these instructions use the L bus (LAB and

LDB), these instructions can access any virtual space handled by the CPU. If these instructions

access the cacheable area while the cache is enabled, the area accessed by these instructions are

cached. The X memory and Y memory are mapped to the virtual address space and can also be

accessed by the single data transfer instructions. In this case, bus conflict may occur between data

transfer and instruction fetch because the CPU also uses the L bus for instruction fetches.

The single data transfer instructions can handle both word and longword data. In word data

transfer, only the upper word of the operand register is valid. In word data load, word data is

loaded into the upper word of the destination registers and the lower word of the destination is

automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage.

In longword data load, longword data is loaded into the upper and lower word of the destination

LDB bus.

Notes: * Since the DSR register is defined as the system register, it can be accessed by the LDS

or STS instruction.

1. Any data transfer instruction is executed at the MA stage of the pipeline.

2. Any data transfer instruction does not modify the condition code bits of the DSR

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