SH7721 datasheet(333/1524 Pages) RENESAS

333 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 271 of 1458

REJ09B0033-0300

Interrupt Source

Interrupt

Code *

Interrupt

Priority

(Initial Value)

IPR

(Bit Numbers)

Priority

within IPR

Setting Unit

Default

Priority

TPU

TPI0

H'D80*

0 to 15 (0)

IPRH (7 to 4)

High

TPI1

H'DA0*

TPI2

H'DC0*

TPI3

H'DE0*

Low

IIC

IICI

H'E00*

0 to 15 (0)

IPRH (3 to 0)



MMC

MMCI0

H'E80*

0 to 15 (0)

IPRI (7 to 4)

High

MMCI1

H'EA0*

MMCI2

H'EC0*

MMCI3

H'EE0*

Low

CMT

CMI

H'F00*

0 to 15 (0)

IPRF (3 to 0)



PCC

PCCI

H'F60*

0 to 15 (0)

IPRI (3 to 0)



SDHI

SDI

H'F80*

0 to 15 (0)

IPRJ (7 to 4)



AFEIF

AFECI

H'FE0*

0 to 15 (0)

IPRJ (3 to 0)



TMU0

TUNI0

H'400*

0 to 15 (0)

IPRA (15 to 12)



TMU1

TUNI1

H'420*

0 to 15 (0)

IPRA (11 to 8)



TMU2

TUNI2

H'440*

0 to 15 (0)

IPRA (7 to 4)



RTC

ATI

H'480*

0 to 15 (0)

IPRA (3 to 0)

High

PRI

H'4A0*

CUI

H'4C0*

Low

SIM

ERI

H'4E0*

0 to 15 (0)

IPRB (7 to 4)

High

RXI

H'500*

TXI

H'520*

TEND

H'540*

Low

WDT

ITI

H'560*

0 to 15 (0)

IPRB (15 to 12)



REF

RCMI

H'580*

0 to 15 (0)

IPRB (11 to 8)



Low

Notes: 1. INTEVT2 code.

2. The code set in INTEVT is as same as INTEVT2.

3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the

correspondence of interrupt level and INTEVT, see table 8.5.

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