SH7721 datasheet(334/1524 Pages) RENESAS

334 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 272 of 1458

REJ09B0033-0300

Table 8.4

Interrupt Exception Handling Sources and Priority (IRL Mode)

Interrupt Source

Interrupt

Code *

Interrupt Priority

(Initial Value)

IPR

(Bit Numbers)

Priority

within IPR

Setting Unit

Default

Priority

NMI

H'1C0*



High

H-UDI

H'5E0*



IRL

IRL3 to RL0=B'0000 H'200*3 15



IRL3 to IRL0=B'0001 H'220*3 14



IRL3 to IRL0=B'0010 H'240*3 13



IRL3 to IRL0=B'0011 H'260*3 12



IRL3 to IRL0=B'0100 H'280*3 11



IRL3 to IRL0=B'0101 H'2A0*3 10



IRL3 to IRL0=B'0110 H'2C0*3 9



IRL3 to IRL0=B'0111 H'2E0*3 8



IRL3 to IRL0=B'1000 H'300*3 7



IRL3 to IRL0=B'1001 H'320*3 6



IRL3 to IRL0=B'1010 H'340*3 5



IRL3 to IRL0=B'1011 H'360*3 4



IRL3 to IRL0=B'1100 H'380*3 3



IRL3 to IRL0=B'1101 H'3A0*3 2



IRL3 to IRL0=B'1110 H'3C0*3 1



IRQ

IRQ4

H'680*

0 to 15 (0)

IPRD (3 to 0)



IRQ5

H'6A0*

0 to 15 (0)

IPRD (7 to 4)



TMU

TMU_SUNI

H'6C0*

0 to 15 (0)

IPRD (11 to 8)



DEI0

H'800*

0 to 15 (0)

IPRE

(15 to 12)

High

DEI1

H'820*

0 to 15 (0)

DMAC

(1)

DEI2

H'840*

0 to 15 (0)

DEI3

H'860*

0 to 15 (0)

Low

LCDC

LCDCI

H'900*

0 to 15 (0)

IPRE (7 to 4)



SSL

SSLI

H'980*

0 to 15 (0)

IPRE (3 to 0)



Low

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