SH7721 datasheet(338/1524 Pages) RENESAS

338 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 276 of 1458

REJ09B0033-0300

8.5

Operation

8.5.1

Interrupt Sequence

The sequence of interrupt operations is described below. Figure 8.3 is a flowchart of the

operations.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,

following the priority levels set in the interrupt priority registers A to J (IPRA to IPRJ). Lower

priority interrupts are held pending. If two of these interrupts have the same priority level or if

multiple interrupts occur within a single module, the interrupt with the highest priority is

selected, according to table 8.3, Interrupt Exception Handling Sources and Priority (IRQ

Mode) and table 8.4, Interrupt Exception Handling Sources and Priority (IRL Mode).

3. The priority level of the interrupt selected by the interrupt controller is compared with the

interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level

is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends

an interrupt request signal to the CPU.

4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in

synchronization with the peripheral clock (P

φ). The CPU receives an interrupt at a break in

instructions.

5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).

6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.

7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.

8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the

vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt

handler may branch with the INTEVT or INTEVT2 value as its offset in order to identify the

interrupt source. This enables it to branch to the handling routine for the individual interrupt

source.

Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by

acceptance of an interrupt in this LSI.

2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an

interrupt source that should have been cleared is not inadvertently accepted again, read

the interrupt source flag after it has been cleared, and then clear the BL bit or execute

an RTE instruction.

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