SH7721 datasheet(342/1524 Pages) RENESAS

342 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 280 of 1458

REJ09B0033-0300

(4) SDRAM interface

• Can set the SDRAM in up to two areas.

• Multiplex output for row address/column address.

• Efficient access by single read/single write.

• High-speed access by bank-active mode.

• Supports an auto-refresh and self-refresh.

• Supports low-power function.

(5) Byte-selection SRAM interface

• Can connect directly to a byte-selection SRAM.

(6) PCMCIA direct interface

• Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver. 4.2

(PCMCIA2.1 Rev 2.1).

• Controls the insertion of the wait state using software.

• Supports the bus sizing function of the I/O bus width (only in little endian mode).

(7) Burst ROM (clock synchronous) interface

• Can connect directly to a burst ROM of the clock synchronous type.

(8) Bus arbitration

• Shares all of the resources with other CPU and outputs the bus enable after receiving the bus

request from external devices.

(9) Refresh function

• Supports the auto-refresh and self-refresh functions.

• Specifies the refresh interval using the refresh counter and clock selection.

• Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).

SH7721 Datasheet(PDF) 342 Page - Renesas Technology Corp