SH7721 datasheet(345/1524 Pages) RENESAS

345 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 283 of 1458

REJ09B0033-0300

9.2

Input/Output Pins

The configuration of pins in this module is shown in table 9.1.

Table 9.1

Pin Configuration

Name

I/O

Function

A25 to A0

Address bus

D31 to D0

I/O

Data bus

Bus cycle start

Asserted when a normal space, burst ROM (clock

synchronous/asynchronous), or PCMCIA is accessed. Asserted by

the same timing as

CAS in SDRAM access.

CS0, CS2 to CS4

Chip select

CS5A/CE2A

Chip select

Active only for address map 1

Corresponds to PCMCIA card select signals D15 to D8 when the

PCMCIA is used.

CS5B/CE1A

Chip select

Corresponds to PCMCIA card select signals D7 to D0 when the

PCMCIA is used.

CS6A/CE2B

Chip select

Active only for address map 1

Corresponds to PCMCIA card select signals D15 to D8 when the

PCMCIA is used.

CS6B/CE1B

Chip select

Corresponds to PCMCIA card select signals D7 to D0 when the

PCMCIA is used.

RD/

Read/write signal

Connects to

WE pins when SDRAM or byte-selection SRAM is

connected.

Read strobe (read data output enable signal)

A strobe signal to indicate the memory read cycle when the

PCMCIA is used.

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