SH7721 datasheet(344/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 282 of 1458

REJ09B0033-0300

The block diagram of the BSC is shown in figure 9.1.

CMNCR

CS0WCR

CS6BWCR

RWTCNT

CS0BCR

CS6BBCR

SDCR

RTCSR

RTCNT

RTCOR

Comparator

Bus

mastership

controller

Wait

controller

Area

controller

Internal master

module

Internal slave

module

Memory

controller

Refresh

controller

Interrupt

controller

[Legend]

BSC

CS0, CS2, CS3,

CS4, CS5A, CS5B,

CS6A, CS6B

WAIT

MD5 to MD3

IOIS16

A25 to A0,

D31 to D0

REFOUT

BACK

BREQ

BS, RD/WR, RD,

WE3(BE3) to WE0(BE0),

RAS, CAS,

CKE, DQMxx,

CE2A, CE2B

CE1A, CE1B

ICIORD, ICIOWR

CMNCR:

CSnWCR:

RWTCNT:

CSnBCR:

SDCR:

RTCSR:

RTCNT:

RTCOR:

Common control register

CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)

Reset wait counter

CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)

SDRAM control register

Refresh timer control/status register

Refresh timer counter

Refresh time constant register

Figure 9.1

Block Diagram of BSC

SH7721 Datasheet(PDF) 344 Page - Renesas Technology Corp

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