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SH7721 Datasheet(PDF) 339 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 339 Page - Renesas Technology Corp |
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339 / 1524 page ![]() Section 8 Interrupt Controller (INTC) Rev. 3.00 Jan. 18, 2008 Page 277 of 1458 REJ09B0033-0300 I3 to I0: Interrupt mask bits in status register (SR) Program execution state Interrupt generated? SR.BL=0, sleep mode, or standby mode? Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No NMI? Level 15 interrupt? Set interrupt source in INTEVT and INTEVT2 Save SR to SSR; save PC to SPC Set BL, MD, and RB bits in SR to 1 Branch to exception handler I3 to I0 levels are 14 or lower? Level 14 interrupt? I3 to I0 levels are 13 or lower? Level 1 interrupt? I3 to I0 levels are 0? Figure 8.3 Interrupt Operation Flowchart |
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