7733 datasheet(368/940 Pages) RENESAS

368 / 940 page

CLOCK GENERATING CIRCUIT

7733 Group User’s Manual

14–5

14.3 Clock control

Figure 14.3.1 shows the clock generating circuit block diagram.

14.3 Clock control

Fig. 14.3.1 Clock generating circuit block diagram

1/8

CM3

CM4

CMi: Bit i at address 6C 16 (Refer to Figure 11.2.2. )

CCi: Bit i at address 6F 16 (Refer to Figure 11.2.3.)

System clock

STP instruction

1/4

1/2

1/8

1/2

f64

f512

f16

f32

Internal

clock

WIT instruction

Reset

Watchdog timer frequency

selection flag

WDC

12-bit

watchdog

timer

1/2

XIN

XOUT

P77/AN7/XCIN

P76/AN6/XCOUT

CC1

CM3

CM5

CM2

CM3

CC1

CM4

CC2

P67/TB2IN/

SUB

(Port latch)

Timer B2

(Event counter mode)

(Clock timer)

(Clock

prescaler)

1/32

fC32

CM4

PC1

Main clock

Sub clock

(Oscillation circuit control register 0: address 6C 16)

CM2: Main clock stop bit

CM3: System clock selection bit

CM4: Port-Xc selection bit

CM5: System clock stop bit at wait state

(Oscillation circuit control register 1: address 6F 16)

CC0: Main clock division selection bit

CC1: Main clock external input selection bit

CC2: Sub clock external input selection bit

(Port function control register: address 6D 16)

PC1: Sub-clock output selection bit/Timer B2 clock source selection bit

CM4

PC1

CC0

CM3

CM4

CM3

Interrupt request

Interrupt disable flag

Switch represented by

is controlled by a signal represented by “

”.

CM4

CC2

CM4

STP instruction

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