7733 datasheet(369/940 Pages) RENESAS

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CLOCK GENERATING CIRCUIT

7733 Group User’s Manual

14–6

14.3 Clock control

14.3.1 Clock generated in clock generating circuit

(1) System clock

It is the clock source of the system clock divided by 2, internal clock

φ, clock φ 1, and clocks f2 to f512.

(Refer to Figure 14.3.1.) Each of the main clock, main clock divided by 8, and the sub clock can be

selected as the system clock by the system clock selection bit (bit 3 at address 6C16). Table 14.3.1

lists clock combinations of the system clock, internal clock

φ, φ 1, and f2.

Port-Xc selection

bit

(bit 4 at 6C16)

System clock

selection bit

(bit 3 at 6C16)

Main clock division

selection bit

(bit 0 at 6C16)

System clock

Table 14.3.1 Clock combinations of system clock, internal clock

φ, φ1, and f2

Internal clock

φ, φ1, f2

(Sub clock is not

used.)

Main clock

Main clock divided by 8

Main clock

Sub clock

Main clock divided by 2

Main clock

Main clock divided by 16

Main clock divided by 8

Main clock divided by 2

Main clock

Sub clock divided by 2

(Sub clock is used.)

(2) Main clock

It is the clock supplied by the main-clock oscillation circuit. This clock is selected as the system clock

immediately after reset.

After the sub clock is selected as the system clock, the main-clock supply is stopped/restarted by the

main clock stop bit (bits 2 at address 6C16). (Refer to Figures 14.3.6 and 14.3.7.)

By stopping the main-clock supply, power consumption can be held down.

Figure 14.3.5 shows the clock f2 state transition when a sub clock is not used because the port-Xc

selection bit (bit 4 at address 6C16) = “0.” During reset and till after reset state is terminated, the main

clock divided by 2 is selected as clock f2. If the system clock selection bit (bit 3 at address 6C16) is

set to “1,” at this time, the main clock divided by 16 is selected as clock f2, and the clock frequency

which is supplied to the CPU and peripheral devices becomes 1/8. Though this slow down the processing

speed, current consumption is held down. Furthermore, by setting “1” to both of the main clock division

selection bit (bit 0 at address 6F16) and system clock selection bit, the main clock divided by 8 is

selected as clock f2.

When the port-Xc selection bit = “0,” clock fC32, which is the main clock divided by 32, is connected

as the timer B2’s count source if the timer B2 clock source selection bit (bit 1 at address 6D16) = “1”

and timer B2 is used as a clock timer. By this, even when the main clock’s ratio is changed, the clock

timer can use the same clock source. (Refer to Figure 14.3.1.)

7733 Datasheet(PDF) 369 Page - Renesas Technology Corp

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