7733 datasheet(370/940 Pages) RENESAS

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CLOCK GENERATING CIRCUIT

7733 Group User’s Manual

14–7

14.3 Clock control

(3) Sub clock

It is the clock supplied by the sub-clock oscillation circuit. The sub-clock supply is stopped immediately

after reset (Note). When the port-Xc selection bit (bit 4 at address 6C16) is set to “1,” the sub-clock

oscillation circuit starts operating, in other words, oscillation starts or an external clock is input.

Furthermore, in this case, fC32 (sub clock divided by 32) is connected. (Refer to section “7.6 Clock

timer.”)

Furthermore, a sub clock can be the system clock by specifying the system clock selection bit after

the oscillation is stabilized. (Refer to Figure 14.3.6.)

The XCOUT pin’s drivability can be lowered by the XCOUT drivability selection bit (bit 0 at address 6C16)

after oscillation of the sub-clock oscillation circuit is stabilized.

By lowering the XCOUT pin’s drivability, power consumption is held down.

When a sub clock is used, in other words, bit 4 at address 6C16 = “1,” sub clock

φSUB is output from

pin P67/TB2IN/

φSUB if the sub-clock output selection bit (bit 1 at address 6D16) is set to “1.”

Note: At this time, the oscillator which is connected to the sub-clock oscillation circuit stops operating,

and pins XCIN and XCOUT function as ports P76 and P77.

(4) Internal clock

It is the CPU’s operating clock source, and its clock source is the system clock.

(5) Clocks f2 to f512

Each of them is the internal peripheral devices’ operating clock, and its clock source is the system

clock.

(6) Clock

φ 1

It is output to external circuits and has the same period as internal clock

φ, and its clock source is

the system clock.

(7) fC32

It is the main clock/sub clock divided by 32 (Refer to Figure 14.3.1.) and the count source of the clock

timer. (Refer to “7.6 Clock timer.”)

(8) Sub clock

φSUB

Sub clock

φSUB is output from port P67 if the sub clock output selection bit (bit 1 at address 6D16) is

set to “1” when the port Xc selection bit = “1,” in other words, when the sub clock is used. Therefore,

the 32-kHz sub clock can be supplied to the external gate.

7733 Datasheet(PDF) 370 Page - Renesas Technology Corp