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7477 Datasheet(PDF) 245 Page - Renesas Technology Corp |
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7477 Datasheet(HTML) 245 Page - Renesas Technology Corp |
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245 / 354 page  7470/7471/7477/7478 GROUP USER’S MANUAL 2-10 APPLICATION 2.3 Timers 7470 7471 7477 7478 ,,,, 2.3 Timers 2.3.1 Memory allocation Figure 2.3.1 shows a memory map of timer related registers. Fig. 2.3.1 Memory map of timer related registers 00F016 00F116 00F716 00F216 00FC16 00FD16 00FE16 00FF16 00D416 00D516 00D616 00F916 00FA16 00FB16 00F816 00F316 Address Edge polarity selection register (EG) Input latch register (ILR) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer FF register (TF) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer mode register 2 (TM2) CPU mode register (CPUM) Interrupt request register 1 (IR1) Interrupt request register 2 (IR2) Interrupt control register 1 (IE1) Interrupt control register 2 (IE2) |
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