EPLD datasheet(11/42 Pages) ALTERA

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Altera Corporation

755

EP610 EPLD

Features

High-performance, 16-macrocell Classic EPLD

–

Combinatorial speeds with tPD as fast as 10 ns

–

Counter frequencies of up to 100 MHz

–

Pipelined data rates of up to 125 MHz

Programmable I/O architecture with up to 20 inputs or 16 outputs

and 2 clock pins

EP610 and EP610I devices are pin-, function-, and programming

file-compatible

Programmable clock option for independent clocking of all registers

Macrocells individually programmable as D, T, JK, or SR flipflops, or

for combinatorial operation

Available in the following packages (see Figure 7):

–

24-pin small-outline integrated circuit (plastic SOIC only)

–

24-pin ceramic and plastic dual in-line package (CerDIP and

PDIP)

–

28-pin plastic J-lead chip carrier (PLCC)

Figure 7. EP610 Package Pin-Out Diagrams

Package outlines not drawn to scale. Windows in ceramic packages only.

28-Pin PLCC

24-Pin SOIC

24-Pin DIP

I/O

EP610

EP610I

EP610

EP610I

EP610

CLK1

INPUT

I/O

INPUT

GND

VCC

INPUT

I/O

INPUT

CLK2

CLK1

INPUT

I/O

INPUT

GND

VCC

INPUT

I/O

INPUT

CLK2

EPLD Datasheet(PDF) 11 Page - Altera Corporation

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