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EPLD Datasheet(PDF) 18 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 18 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Tables 10 and 11 show the timing parameters for EP610-25, EP610-30 and
EP610-35 devices.
tSU
Register setup time
5.0
4.0
ns
tH
Register hold time
4.0
7.0
ns
tIC
Array clock delay
6.0
11.0
ns
tICS
Global clock delay
2.0
4.0
ns
tFD
Feedback delay
1.0
1.0
ns
tCLR
Register clear time
6.0
11.0
ns
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20
Unit
Min Max Min Max
Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
EP610-25
EP610-30
EP610-35 Non-Turbo
Adder
Unit
Min Max Min Max Min Max
(3)
tPD1
Input to non-registered output
C1 = 35 pF
25.0
30.0
35.0
30.0
ns
tPD2
I/O input to non-registered output
27.0
32.0
37.0
30.0
ns
tPZX
Input to output enable
25.0
30.0
35.0
30.0
ns
tPXZ
Input to output disable
C1 = 5 pF
(4)
25.0
30.0
35.0
30.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
27.0
32.0
37.0
30.0
ns
fMAX
Maximum frequency
(5)
47.6
41.7
37.0
0.0
MHz
tSU
Global clock input setup time
21.0
24.0
27.0
30.0
ns
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
10.0
11.0
12.0
0.0
ns
tCL
Global clock low time
10.0
11.0
12.0
0.0
ns
tCO1
Global clock to output delay
15.0
17.0
20.0
0.0
ns
tCNT
Global clock minimum period
25.0
30.0
35.0
0.0
ns
fCNT
Maximum internal global clock
frequency
(6)
40.0
33.3
28.6
0.0
MHz
tASU
Array clock input setup time
8.0
8.0
8.0
30.0
ns
tAH
Array clock input hold time
12.0
12.0
12.0
0.0
ns
tACH
Array clock high time
10.0
11.0
12.0
0.0
ns
tACL
Array clock low time
10.0
11.0
12.0
0.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(7)
1.0
1.0
1.0
ns
tACO1
Array clock to output delay
27.0
32.0
37.0
30.0
ns
tACNT
Array clock minimum period
25.0
30.0
35.0
0.0
ns
fACNT
Maximum internal global clock
frequency
(6)
40.0
33.3
28.6
0.0
MHz



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