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EPLD Datasheet(PDF) 35 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 35 Page - Altera Corporation

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Altera Corporation
779
Classic EPLD Family Data Sheet
Figure 16. EP1810 Block Diagram
Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages.
(K4)
(L4)
(K5)
(L5)
(L6)
(K7)
(L7)
(K8)
INPUT
INPUT
INPUT
INPUT/CLK1
INPUT/CLK2
INPUT
INPUT
INPUT
(B4) 56
(A5) 55
(B5) 54
(A6) 53
(A7) 51
(B7) 50
(A8) 49
(B8) 48
INPUT
INPUT
INPUT
INPUT/CLK4
INPUT/CLK3
INPUT
INPUT
INPUT
Quadrant A
(F1)
(G2)
(G1)
(H2)
(H1)
(J2)
(J1)
(K1)
(K2)
(L2)
(K3)
(L3)
Macrocell 48
Macrocell 47
Macrocell 46
Macrocell 45
Macrocell 44
Macrocell 43
Macrocell 42
Macrocell 41
Macrocell 40
Macrocell 39
Macrocell 38
Macrocell 37
Quadrant D
(E1) 68
(E2) 67
(D1) 66
(D2) 65
(C1) 64
(C2) 63
(B1) 62
(B2) 61
(A2) 60
(A3) 59
(B3) 58
(A4) 57
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
(L8)
(K9)
(L9)
(L10)
(K10)
(K1
1)
(J10)
(J11)
(H10)
(H1
1)
(G10)
(G1
1)
Macrocell 36
Macrocell 35
Macrocell 34
Macrocell 33
Macrocell 32
Macrocell 31
Macrocell 30
Macrocell 29
Macrocell 28
Macrocell 27
Macrocell 26
Macrocell 25
(A9) 47
(B9) 46
(A10) 45
(B10) 44
(B11) 43
(C11) 42
(C10) 41
(D11) 40
(D10) 39
(E11) 38
(E10) 37
(F11) 36
Quadrant B
Quadrant C
Global Macrocells
Local Macrocells
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Global
Bus
2
3
4
5
6
7
8
9
10
11
12
13
23
24
25
26
27
28
29
30
31
32
33
34
14
15
16
17
19
20
21
22



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