EPLD datasheet(12/42 Pages) ALTERA

12 / 42 page

756

Altera Corporation

Classic EPLD Family Data Sheet

General

Description

EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,

and 2 global clock pins (see Figure 8). Each macrocell can access signals

from the global bus, which consists of the true and complement forms of

the dedicated inputs and the true and complement forms of either the

output of the macrocell or the I/O input. The CLK1 signal is a dedicated

global clock input for the registers in macrocells 9 through 16. The CLK2

signal is a dedicated global clock input for registers in macrocells 1

through 8.

Figure 8. EP610 Block Diagram

Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.

Figure 9 shows the typical supply current (ICC) versus frequency of EP610

devices.

Figure 9. ICC vs. Frequency of EP610 Devices

(26)

(25)

(24)

(23)

(22)

(21)

(20)

(18)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(12)

2 (3)

1 (2)

INPUT

CLK1

(13)

INPUT

(27)

(16)

INPUT

CLK2

Global

Bus

(17)

INPUT

Macrocell 9

Macrocell 10

Macrocell 11

Macrocell 12

Macrocell 13

Macrocell 14

Macrocell 15

Macrocell 16

Macrocell 1

Macrocell 2

Macrocell 3

Macrocell 4

Macrocell 5

Macrocell 6

Macrocell 7

Macrocell 8

Frequency

1 kHz

10 kHz 100 kHz 1 MHz 10 MHz

80 MHz

0.1

1.0

100

Turbo

Non-Turbo

VCC = 5.0 V

TA = 25° C

Typical I

Active (mA)

EPLD Datasheet(PDF) 12 Page - Altera Corporation

EPLD Datasheet(HTML) 12 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL