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EPLD Datasheet(PDF) 40 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 40 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Table 30. EP1810-35 & EP1810-45 External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
EP1810-35 EP1810-45
Non-Turbo
Adder
Unit
Min Max Min Max
(2)
tPD1
Input to non-registered output
C1 = 35 pF
35.0
45.0
30.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
40.0
50.0
30.0
ns
tSU
Global clock setup time
25.0
30.0
30.0
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
12.0
15.0
0.0
ns
tCL
Global clock low time
12.0
15.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
20.0
25.0
0.0
ns
tCNT
Minimum global clock period
(3)
35.0
45.0
0.0
ns
fCNT
Maximum internal frequency
(3)
28.6
22.2
0.0
MHz
tASU
Array clock setup time
10.0
11.0
30.0
ns
tAH
Array clock hold time
15.0
18.0
0.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
35.0
45.0
30.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(4)
1.0
1.0
ns
tACNT
Array clock maximum clock period
(3)
35.0
45.0
0.0
ns
fACNT
Maximum internal array clock
frequency
(3)
28.6
22.2
0.0
ns
fMAX
Maximum clock frequency
(5)
40
33.3
0.0
MHz
Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters
Symbol
Parameter
Conditions
EP1810-35 EP1810-45
Non-Turbo
Adder
Unit
Min Max Min Max
(2)
tIN
Input pad and buffer delay
7.0
6.0
0.0
ns
tIO
I/O input pad and buffer delay
5.0
5.0
0.0
ns
tLAD
Logic array delay
19.0
28.0
30.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
9.0
11.0
0.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
9.0
11.0
0.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
(6)
9.0
11.0
0.0
ns
tSU
Register setup time
10.0
10.0
0.0
ns
tH
Register hold time
15.0
18.0
0.0
ns
tIC
Array clock delay
19.0
28.0
30.0
ns
tICS
Global clock delay
4.0
8.0
0.0
ns
tFD
Feedback delay
6.0
7.0
–30.0
ns
tCLR
Register clear time
24.0
32.0
30.0
ns



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