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EPLD Datasheet(PDF) 34 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 34 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
General
Description
Altera EP1810 devices offer LSI density, TTL-equivalent speed, and low-
power consumption. EP1810 devices have 48 macrocells, 16 dedicated
input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided
into four quadrants, each containing 12 macrocells. Of the 12 macrocells
in each quadrant, 8 have quadrant feedback and are “local” macrocells
(see “Feedback Select” on page 749 of this data sheet for more
information). The remaining 4 macrocells in the quadrant are “global”
macrocells. Both local and global macrocells can access signals from the
global bus, which consists of the true and complement forms of the
dedicated inputs and the true and complement forms of the feedbacks
from the global macrocells.
EP1810 devices also have four dedicated inputs (one in each quadrant)
that can be used as quadrant clock inputs. If the dedicated input is used
as a clock pin, the input feeds the clock input of all registers in that
particular quadrant.



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