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EPLD Datasheet(PDF) 17 Page - Altera Corporation

Part # EPLD
Description  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 17 Page - Altera Corporation

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Altera Corporation
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Classic EPLD Family Data Sheet
Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20
devices.
Table 8. EP610-15 & EP610-20 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
EP610-15
EP610-20
Non-Turbo
Adder
Unit
Min Max Min Max
(3)
tPD1
Input to non-registered output
C1 = 35 pF
15.0
20.0
20.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
17.0
22.0
20.0
ns
tPZX
Input to output enable
C1 = 35 pF
15.0
20.0
20.0
ns
tPXZ
Input to output disable
C1 = 5 pF
(4)
15.0
20.0
20.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
15.0
20.0
20.0
ns
fMAX
Maximum clock frequency
(5)
83.3
62.5
0.0
MHz
tSU
Global clock input setup time
9.0
11.0
20.0
ns
tH
Global clock input hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
6.0
8.0
0.0
ns
tCL
Global clock low time
6.0
8.0
0.0
ns
tCO1
Global clock to output delay
11.0
13.0
0.0
ns
tCNT
Global clock minimum period
12.0
16.0
0.0
ns
fCNT
Maximum internal global clock
frequency
(6)
83.3
62.5
0.0
MHz
tASU
Array clock input setup time
6.0
8.0
20.0
ns
tAH
Array clock input hold time
6.0
8.0
0.0
ns
tACH
Array clock high time
7.0
9.0
0.0
ns
tACL
Array clock low time
7.0
9.0
0.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(7)
1.0
1.0
1.0
ns
tACO1
Array clock to output delay
15.0
20.0
20.0
ns
tACNT
Array clock minimum period
14.0
18.0
0.0
ns
fACNT
Array clock internal maximum
frequency
(6)
71.4
55.6
0.0
MHz
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20
Unit
Min Max Min Max
tIN
Input pad and buffer delay
4.0
4.0
ns
tIO
I/O input pad and buffer delay
2.0
2.0
ns
tLAD
Logic array delay
6.0
11.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
5.0
5.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
5.0
5.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
5.0
5.0
ns



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