ATAR092 datasheet(32/107 Pages) ATMEL

32 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

Figure 5-9.

Timer 1 and Watchdog

5.3.1.1

Timer 1 Control Register 1 (T1C1)

Bit 3 = MSB, Bit 0 = LSB

The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on this

divider and the Timer 1 input clock source. The timer input can be supplied by the system clock,

the 32-kHz oscillator or via clock management. If the clock management generates the SUBCL,

the selected input clock from the RC-oscillator, 4-MHz oscillator or an external clock is divided

by 16.

CL1

RES

Q11

Q14

Q11

Q14

T1MUX

SUBCL

T1RM T1C2

T1C1

T1C1 T1C0

T1C2

T1BP T1IM

Decoder

MUX for Interval Timer

Decoder

MUX for Watchdog Timer

WDL WDR WDT1

WDC

WDT0

Write of the

T1C1 Register

Read of the

CWD Register

Watchdog

Mode Control

RES

WDCL

Divider

RESET

(NRST)

T1OUT

INT2

Watchdog

Divider/8

T1IM = 1

T1IM = 0

Address: '7'hex - Subaddress: '8'hex

Bit 3

Bit 2

Bit 1

Bit 0

T1C1

T1RM

T1C2

T1C1

T1C0

Reset value: 1111b

T1RM

Timer 1 Restart Mode

T1RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note: if WDL = 0, Timer 1 restart is impossible

T1C2

Timer 1 Control bit 2

T1C1

Timer 1 Control bit 1

T1C0

Timer 1 Control bit 0

ATAR092 Datasheet(PDF) 32 Page - ATMEL Corporation

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