ATAR092 datasheet(33/107 Pages) ATMEL

33 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

5.3.1.2

Timer 1 Control Register 2 (T1C2)

Bit 3 = MSB, Bit 0 = LSB

5.3.1.3

Watchdog Control Register (WDC)

Bit 3 = MSB, Bit 0 = LSB

Table 5-6.

Timer 1 Control Bits

T1C2

T1C1

T1C0

Divider

Time Interval with

SUBCL

Time Interval with

SUBCL = 32 kHz

Time Interval with

SYSCL = 2/1 MHz

SUBCL/2

61 µs

1 µs/2 µs

SUBCL/4

122 µs

2 µs/4 µs

SUBCL/8

244 µs

4 µs/8 µs

SUBCL/16

488 µs

8 µs/16 µs

SUBCL/32

0.977 ms

16 µs/32 µs

256

SUBCL/256

7.812 ms

128 µs/256 µs

2048

SUBCL/2048

62.5 ms

1024 µs/2048 µs

16384

SUBCL/16384

500 ms

8192 µs/16384 µs

Address: ’7’hex - Subaddress: ’9’hex

Bit 3

Bit 2

Bit 1

Bit 0

T1C2

–

T1BP

T1CS

T1IM

Reset value: x111b

T1BP

Timer 1 SUBCL ByPassed

T1BP = 1, TIOUT = T1MUX

T1BP = 0, T1OUT = SUBCL

T1CS

Timer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see Figure 5-8 on page 31)

T1CS = 0, CL1 = SYSCL (see Figure 5-8 on page 31)

T1IM

Timer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interrupt

T1IM = 0, enables Timer 1 interrupt

Address: ’7’hex - Subaddress: ’A’hex

Bit 3

Bit 2

Bit 1

Bit 0

WDC

WDL

WDR

WDT1

WDT0

Reset value: 1111b

WDL

WatchDog Lock mode

WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no

effect. After the WDL-bit is cleared, the watchdog is active until a system

reset or power-on reset occurs.

WDR

WatchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabled

WDR = 0, the watchdog is active/enabled

ATAR092 Datasheet(PDF) 33 Page - ATMEL Corporation

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