ATAR092 datasheet(48/107 Pages) ATMEL

48 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

Figure 5-24. Counter 3 Stage

The status of the timer as well as the occurrence of a compare match or an edge detect of the

input signal is indicated by the status register T2ST. This allows identification of the interrupt

source because all these events share only one timer interrupt.

Timer 3 compares data values

The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value can be

‘m’ for each of the Timer 3 compare registers.

The compare data value for the compare registers is:

m = x +1

≤ x ≤ 255

Timer 3 – Mode 1:

Timer/Counter

The selected clock from an internal or external source increments the 8-bit counter. In this mode,

the timer can be used as event counter for external clocks at T3I or as timer for generating inter-

rupts and pulses at T3O. The counter value can be read by the software via the capture register.

Figure 5-25. Counter Reset with Each Compare Match

T3TM1

T3IM1

TOG2 T3I

Control

CL3

RES

C31

CM32

CM31

C32

8-bit Counter

Capture Register

8-bit Comparator

Control

Compare Register 2

Compare Register 1

TOG3

INT5

T3RM1

T3EIM

T3SM1

T3TM2

: T3M1

: T3M2

T3IM2

T3RM2

T3SM2

Counter 3

INT5

T3O

CM32

CM31

T3R

ATAR092 Datasheet(PDF) 48 Page - ATMEL Corporation

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