ATAR092 datasheet(46/107 Pages) ATMEL

46 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

5.3.3

Timer 3

5.3.3.1

Features

• 2 compare registers

• Capture register

• Edge sensitive input with zero cross detection capability

• Trigger and single action modes

• Output control modes

• Automatically modulation and demodulation modes

• FSK modulation

• Pulse width Modulation (PWM)

• Manchester demodulation together with SSI

• Bi-phase demodulation together with SSI

• Pulse-width demodulation together with SSI

Figure 5-23. Timer 3

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The

timer can be used as event counter, timer and signal generator. Its output can be programmed

as modulator and demodulator for the serial interface. The two compare registers enable various

modes of signal generation, modulation and demodulation. The counter can be driven by inter-

nal and external clock sources. For external clock sources, it has a programmable

edge-sensitive input which can be used as counter input, capture signal input or trigger input.

This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU

core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via

its capture register while it is running. In capture mode, the counter value can be captured by a

programmable capture event from the Timer 3 input or Timer 2 output.

I/O-bus

8-bit Counter 3

T3CS

T3CP

T3CO1

T3CO2

T3C

T3ST

T3CM1

T3CM2

Compare 3/1

CL3

CP3

POUT

T3EX

SYSCL

T1OUT

RES

T3I

Timer 2

SSI

Modulator 3

Compare 3/2

Control

TOG3

T3I

T3EX

RES

CM31

INT5

T3O

Control

SCI

T3M

Demodu-

lator 3

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