ATAR092 datasheet(63/107 Pages) ATMEL

63 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the

incoming serial data is shifted into the shift register. This first telegram is automatically trans-

ferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer contains

valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shift-

ing in the following 8-bit telegram. If, during this time the first telegram has been read by the

controller, the second telegram will also be transferred in the same way into the receive buffer

and the SSI will continue clocking in the next telegram. Should, however, the first telegram not

have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in

the shift register until a certain point of time when the controller is able to service the receive

buffer. In this way no data is lost or overwritten.

Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the

present contents of the shift register into the receive buffer. This can be used for clocking in a

data telegram of less than 8 bits in length. Care should be taken to read out the final complete

8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and termi-

nating the reception. After termination, the shift register contents will overwrite the receive

buffer.

Figure 5-39. Example of 8-bit Synchronous Transmit Operation

tx data 1

Write STB

(tx data 1)

Write STB

(tx data 2)

Write STB

(tx data 3)

msb

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

SIR

lsb

65 4 3 2

76 5 4 3 2

tx data 2

tx data 3

msb

lsb msb

lsb

ATAR092 Datasheet(PDF) 63 Page - ATMEL Corporation

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