GRSPW datasheet(22/48 Pages) ACTEL

22 / 48 page

GRSPW / GRSPW-FT

December 2008, Version 1.0.2

GAISLER

clock network. The specific type of clock network depends on the technology used. The xor gate is

actually all that logically belongs to the Rx clock recovery module in figure 8.

The clock output drives all flip-flops in the receiver module found in figure 4. The data signal which

is used for generating the clock is also coupled to the data inputs of several flip-flops clocked by the

Rx clock as seen in figure 8. Care must be taken so that the delay from the data and strobe signals

through the clock network are longer than the delay to the data input + setup time.

The transmitter clock is generated from the txclk input. A separate clock input is used to allow the

transmitter to be run at much higher frequencies than the system clock. The SpaceWire node contains

a clock-divider which divides the txclk signal to the wanted frequency. The transmitter clock should

be 10 MHz during initialization and any frequency above 2 MHz in the run-state.

There is an input signal called clkdiv10 which sets the clock divisor value during initialization and the

reset value for the user accessible clock divisor register. The user register value will be used in run-

state. The resulting tx clock frequency will be txclk/(clock divisor value+1). So if no clock division is

wanted, the clock divisor should be set to 0.

Since only integer values are allowed for the clock division and the required init-frequency is 10 Mhz

the frequency of the txclk input must be a multiple of 10 MHz. The clock divisor value is 8-bits wide

so the maximum txclk frequency supported is 2.56 GHz (note that there is also a restriction on the

relation between the system and transmit clock frequencies).

2.8.2

Timers

There are two timers in the core: one for generating the 6.4/12.8 us periods and one for disconnect

timing. The system clock frequency must be at least 10 MHz to guarantee disconnect timing limits.

There are two user accessible registers which are used to the set the number of clock cycles used for

the timeout periods. These registers are described in section 2.9.

The reset value for the timer registers can be set in two different ways selected by the usegen VHDL

generic. If usegen is set to 1, the sysfreq VHDL generic is used to generate reset values for the discon-

nect, 6.4 us and 12.8 us timers. Otherwise, the input signals dcrstval and timerrstval will be used as

reset values. If the system clock frequency is 10 MHz or above the disconnect time will be within the

limits specified in the SpaceWire standard.

2.8.3

Synchronization

The VHDL generic nsync selects how many synchronization registers are used between clock

domains. The default is one and should be used when maximum performance is needed. It allows the

transmitter to be clocked 4 times faster than the system clock and the receiver 2 times faster. These are

Figure 8. The clocking scheme for the receiver. The clock is generated

GRSPW Datasheet(PDF) 22 Page - Actel Corporation