GRSPW datasheet(32/48 Pages) ACTEL

32 / 48 page

GRSPW / GRSPW-FT

December 2008, Version 1.0.2

GAISLER

2.12

Signal descriptions

Table 27 shows the interface signals of the core (VHDL ports).

2.13

Library dependencies

Table 28 shows libraries used when instantiating the core (VHDL libraries).

2.14

Instantiation

This example shows how the core can be instantiated.

Normally di, si, do and so should be connected to input and output pads configured with LVDS driv-

ers. How this is done is technology dependent.

The GRSPW in the example is configured with non-ft memories of size 4, 64 and 8 entries for AHB

FIFOs, N-Char FIFO and RMAP buffers respectively. The system frequency (clk) is 40 MHz and the

transmitter frequency (txclk) is 20 MHz.

Table 27. Signal descriptions

Signal name

Field

Type

Function

Active

RST

N/A

Input

Reset

Low

CLK

N/A

Input

Clock

TXCLK

N/A

Input

Transmitter default run-state clock

AHBMI

Input

AMB master input signals

AHBMO

Output

AHB master output signals

APBI

Input

APB slave input signals

APBO

Output

APB slave output signals

SWNI

Input

Data input

Input

Strobe input

TICKIN

Input

Time counter tick input

High

CLKDIV10

Input

Clock divisor value used during initialization

and as reset value for the clock divisor register

RMAPEN

Input

Reset value for the rmapen control register bit

DCRSTVAL

Input

Reset value for disconnect timer. Used if usegen

VHDL generic is set to 0.

TIMERRSTVAL

Input

Reset value for 6.4 us timer. Used if usegen

VHDL generic is set to 0.

SWNO

Output

Data output

Output

Strobe output

TICKOUT

Output

Time counter tick output

High

* see GRLIB IP Library User’s Manual

Table 28. Library dependencies

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA signal definitions

GAISLER

SPACEWIRE

Signals, component

Component and record declarations.

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