LTC2484CDD datasheet(15/40 Pages) LINER

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LTC2484

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APPLICATIO S I FOR ATIO

Temperature Sensor (IM)

The LTC2484 includes an on-chip temperature sensor. The

temperature sensor is selected by setting IM = 1 in the serial

input data stream. Conversions are performed directly on

the temperature sensor by the converter. While operating

in this mode, the device behaves as a temperature to bits

converter. The digital reading is proportional to the

absolute temperature of the device. This feature allows the

converter to linearize temperature sensors or continuously

remove temperature effects from external sensors. Several

applications leveraging this feature are presented in more

detail in the applications section. While operating in

this mode, the speed is set to normal independent of

control bit SPD.

Rejection Mode (FA, FB)

The LTC2484 includes a high accuracy on-chip oscillator

with no required external components. Coupled with a 4th

order digital lowpass filter, the LTC2484 rejects line fre-

quency noise. In the default mode, the LTC2484 simulta-

neously rejects 50Hz and 60Hz by at least 87dB. The

LTC2484 can also be configured to selectively reject 50Hz

or 60Hz to better than 110dB.

Speed Mode (SPD)

The LTC2484 continuously performs offset calibrations.

Every conversion cycle, two conversions are automati-

cally performed (default) and the results combined. This

result is free from offset and drift. In applications where

the offset is not critical, the autocalibration feature can be

disabled with the benefit of twice the output rate.

Linearity, full-scale accuracy, full-scale drift are identical for

both 2x and 1x speed modes. In both the 1x and 2x speed

there is no latency. This enables input steps or multiplexer

channel changes to settle in a single conversion cycle easing

system overhead and increasing the effective conversion

rate.

Output Data Format

The LTC2484 serial output data stream is 32 bits long. The

first 3 bits represent status information indicating the sign

and conversion state. The next 24 bits are the conversion

result, MSB first. The remaining 5 bits are sub LSBs below

the 24-bit level. The third and fourth bit together are also

used to indicate an underrange condition (the differential

input voltage is below –FS) or an overrange condition (the

differential input voltage is above +FS).

CS may be pulled high prior to outputting all

32 bits, aborting the data out transfer and initiating a new

conversion.

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

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