LTC2484CDD datasheet(24/40 Pages) LINER

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LTC2484

2484fa

APPLICATIO S I FOR ATIO

Whenever SCK is LOW, the LTC2484’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certain applications may require an external driver on SCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2484’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH once

the external driver goes Hi-Z. On the next CS falling edge,

the device will remain in the internal SCK timing mode.

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

period defined above as tEOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

internal pull-up may not be adequate to return SCK to a

HIGH level before CS goes low again. This is not a concern

under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 3-Wire I/O,

Continuous Conversion

This timing mode uses a 3-wire interface. The conversion

result is shifted out of the device by an internally generated

serial clock (SCK) signal, see Figure 10. CS may be perma-

nently tied to ground, simplifying the user interface or

transmission over an isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 1ms after VCC exceeds 2V. An internal weak

pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

Figure 9. Internal Serial Clock, Reduce Data Output Length

DON’T CARE

FOA

FOB

SPD

SDI

DON’T CARE

SDO

SCK

(INTERNAL)

>tEOCtest

MSB

SIG

BIT 8

TEST EOC

(OPTIONAL)

TEST EOC

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA

OUTPUT

CONVERSION

SLEEP

2484 F09

<tEOCtest

TEST EOC

VCC

VREF

IN+

IN–

SCK

SDI

SDO

GND

210

INT/EXT CLOCK

10k

VCC

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUT

µF

2.7V TO 5.5V

LTC2484

4-WIRE

SPI INTERFACE

LTC2484CDD Datasheet(PDF) 24 Page - Linear Technology

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