PCI1450 datasheet(51/132 Pages) TI

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

secondary status register

Bit

Name

Secondary status

Type

R/WC

Default

Secondary status

Type:

Read-only, Read/Write to Clear

Offset:

16h

Default:

0200h

Description: This register is compatible with the PCI-PCI bridge secondary status register. It indicates

CardBus related device information to the host system. This register is very similar to the PCI

status register (offset 06h), and status bits are cleared by a writing a 1. This register is not

shared by the two socket functions, but is accessed on a per socket basis.

Table 26. Secondary Status Register Description

BIT

TYPE

FUNCTION

R/WC

CBPARITY. Detected parity error. This bit is set when a CardBus parity error is detected; either address or data parity errors.

Write a 1 to clear this bit.

R/WC

CBSERR. Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI1450 does not assert

the CSERR signal. Write a 1 to clear this bit.

R/WC

CBMABORT. Received master abort. This bit is set when a cycle initiated by the PCI1450 on the CardBus bus has been

terminated by a master abort. Write a 1 to clear this bit.

R/WC

REC_CBTA. Received target abort. This bit is set when a cycle initiated by the PCI1450 on the CardBus bus was terminated

by a target abort. Write a 1 to clear this bit.

R/WC

SIG_CBTA. Signaled target abort. This bit is set by the PCI1450 when it terminates a transaction on the CardBus bus with

a target abort. Write a 1 to clear this bit.

10–9

CB_SPEED. CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b indicating that the

PCI1450 asserts this signal at a medium speed.

R/WC

CB_DPAR. CardBus data parity error detected. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met.

1 = A data parity error occurred and the following conditions were met:

a. CPERR was asserted on the CardBus interface.

b. The PCI1450 was the bus master during the data parity error.

c. The parity error response bit is set in the

bridge control register.

CBFBB_CAP. Fast back-to-back capable. The PCI1450 cannot accept fast back-to-back transactions; therefore, this bit

is hardwired to 0.

CB_UDF. User definable feature support. The PCI1450 does not support the user definable features; therefore, this bit is

hardwired to 0.

CB66MHZ. 66 MHz capable. The PCI1450 CardBus interface operates at a maximum CCLK frequency of 33 MHz;

therefore, this bit is hardwired to 0.

4–0

Reserved. These bits return 0s when read.

PCI1450 Datasheet(PDF) 51 Page - Texas Instruments

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